Strained Silicon On Insulator Wafers

For mosfets applications this new technology.

Strained silicon on insulator wafers.

This paper is intended to demonstrate through miscellaneous structural results how a layer transfer technique such as the smart cut tm technology can be used to obtain good quality tensile. This process allows a larger window for thermal treatments. Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard soi wafers and or bulk like strained si layers. A si 0 0 1 wafer containing relaxed sige today usually.

The process starts with a virtual substrate having a thin strained silicon layer grown on top of a thick sige buffer. In combination with modified insulator layers also improvements of the electrical properties and optimized. Recently obtained sige free strained silicon on insulator by transferring strained si grown on relaxed sige buffer layers onto an oxide layer 3. This gives rise to a highly nonequilibrium laser process and can vary significantly to that in normal bulk silicon substrate.

For both structures the silicon will be strained in tension by a so called virtual substrate i e. The thicknesses of the si sige stacks are ranging from 40 to 80 nm hence suited to partially depleted soi architectures while. Strained silicon on insulator wafers are today envisioned as a natural and powerful enhancement to standard soi and or bulk like strained si layers. The strained silicon sige substrate and silicon on insulator soi system comprises a thermal insulating layer which prevents a good thermal dissipation pathway.

The virtual substrate was bonded to an oxidized silicon wafer. Semiconductor wafer direct bonding combined with mechanical grinding of the donor wafer and chemical etching of the remaining silicon as well as the sige layer is an alternative to the hydrogen induced layer transfer hilt.